1/2/2023 0 Comments Xilinx ise 14.6 add a bus# Don't regenerate cores for -107,16 +113,19 xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd Xfile add ipcore_dir/internalTriggerGenerator.xco Xfile add -85,7 +91,7 exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_di Xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd #xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd #xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd #xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd Xfile add ipbus/firmware/slaves/hdl/ipbus_reg_v.vhd Xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd ![]() Xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd Xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd + - Execute the build_bitstream.sh -68,6 +68,12 xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd + - Make sure the top-level file is selected and click on "Generate Programming File" + - When Coregen starts select Project->Upgrade and Regenerate all project IP ( this will take several minutes ) + - Open the Xilinx project file at /workspace/fmc-mtlu.xise ![]() This will check out copies of the IPBus and AIDA mini-TLU repositories,Ĭreate a directory for the files produced by firmware synthesise Execute the script to set-up the ISE project: + Edit setup_workspace.sh to reflect which FPGA carrier board you want to build the firmware for.Currently supported boards: Xilinx SP601, Xilinx SP605. Install Xilinx ISE 14.6 (or newer) and set up the environment variables.Ģ. Version-management control with files generated by core regeneration process.įirmware build scripts may work under Windows/Cygwin or Windows/MinGWġ. Standard Xilinx auto-generated ones "contaminate" directories that are under Needs "IPBus" to communuicate via Ethernet to host. Tri_mode_eth_mac ) if using an external Physical interface chip ![]() Needs a licence for the Xilinx Gigabit ethernet soft core ( Uses the "IPBus" system to communuicate via Ethernet to host. _designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd +4 -4įirmware/scripts/aida_mini_tlu_addr_map.txt +5 -1įirmware/scripts/test_aida_tlu_thresholds.py +14 -5įirmware/scripts/test_aida_tlu_trig_counter.py +93 -0įirmware/simulation/questa/fmctlu_v0_1_testbench.fdo +115 -0įirmware/simulation/questa/fmctlu_v0_1_testbench.udo +10 -0įirmware/simulation/questa/fmctlu_v0_1_testbench_wave.fdo +12 -0įirmware/simulation/questa/modelsim.ini +1868 -0įirmware/simulation/scripts/addfiles_sim.tcl +38 -0įirmware/simulation/scripts/file_list +67 -0įirmware/simulation/scripts/setup.sh +12 -0įirmware/simulation/scripts/setup_project.tcl +24 -0įirmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd +182 -0įirmware/simulation_src/pmtPulseGenerator_rtl.vhd +152 -0įirmware for AIDA miniTLU are/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd +3 -0 Firmware/config/ise14/sp601/build_bitstream.tcl +1 -1įirmware/config/ise14/sp601/setup_project.tcl +15 -6įirmware/config/ise14/sp605/build_bitstream.tcl +1 -1įirmware/config/ise14/sp605/setup_project.tcl +12 -5įirmware/hdl/common/IPBusInterface_rtl.vhd +3 -5įirmware/hdl/common/clocks_s6_extphy.vhd +2 -1įirmware/hdl/common/counterWithReset_rtl.vhd +1 -1įirmware/hdl/common/dualSERDES_1to4_rtl.vhd +43 -40įirmware/hdl/common/eventBuffer_rtl.vhd +10 -4įirmware/hdl/common/ipbus_addr_decode.vhd +0 -2įirmware/hdl/common/logic_clocks_rtl.vhd +73 -90įirmware/hdl/common/triggerInputs_rtl.vhd +80 -21įirmware/hdl/test/clock_divider_s6.v +2 -1
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